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AttributeArty A7Tang Mega 60K Dock
FPGAXC7A35TICSG324-1LGW5AT-LV60PG484AC1/I0
FamilyArtix-7GW5A
Logic (LUTs)not listed59904
Priceat the sellerat the seller
Open toolchainProject X-Ray / openXC7no
ToolchainsVivado WebPACK / ML StandardGowin EDA, LiteX (litex-boards sipeed_tang_mega_60k), openFPGALoader (GW5AT-60)
InterfacesEthernet, USB UART, USB-JTAGPCIe 2.0 card-edge (x1 mode only at present), USB 3.0 (CH569, 5 Gbps), Gigabit Ethernet, HDMI/DVI (TX and RX), SD slot (1-bit SDIO/MMC or SPI), USB JTAG, USB UART, Differential ADC channels
MemoryDDR3 variant-specific; verify in Digilent memory tabDDR3 4 Gbit (512 MB), Onboard flash 64 Mbit
LevelBeginnerProfessional
Where to get helpDigilent ForumSipeed forum, r/GowinFPGA
Known issues35T and 100T variants differPCIe works in x1 mode only; Minimum Gowin IDE version; 3.3 V I/O limit

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