AMD is sampling the Versal AI Core XQRVC1902 with early access customers in a lidless space-grade package with an organic substrate. Class Y testing i…
FPGA.camp
FPGA news and engineering
Tool releases, RTL articles and community projects.
News
FPGA feed
Orthogone released a licensed Ethernet MAC/PCS, TCP/UDP offload and PCIe DMA IP kit for AMD UltraScale+ and Versal. RTL is delivered encrypted; no pri…
RetroRGB covers a full teardown of the ModRetro M64, built on an AMD Artix UltraScale+ FPGA, and the unofficial OM64 firmware that aims to replace the…
AMD announced Ross on 30 September 2026: MCP servers, a documentation knowledge base and open markdown skills for AMD Embedded tools. It works with an…
Lattice will demo Lattice Prompt and Holoscan Sensor Bridge on 6 October, give a security talk, and run a hands-on Nexus and Lattice Prompt workshop o…
At OCP Global Summit 2026 in San Jose (12–15 October), Lattice and AMI will show an open control plane for AI infrastructure: a keynote on 13 October…
Efinix announced Sapphire RV64 on 28 September 2026: a configurable 64-bit RISC-V core with an optional SV39 MMU for Linux and DDR3, LPDDR4x and Hyper…
On 28 September 2026 Al Williams opened The FPGA Chronicles on Hackaday: an updated FPGA Bootcamp built around the Sipeed Tang Nano 20K board with a G…
Yosys 0.69 removes several synthesis passes and adds a SystemVerilog 2023 option to its Verific integration.
LiteX 2026.08, 24 September 2026: Cyclone V and Agilex HPS, Gowin AE350, AXI HyperRAM, new LiteEth PHYs, LitePCIe fixes, Tang Mega 60K and ModRetro M6…
CERN has released colibri for everyone: more than 100 RTL components in VHDL-2008 with self-checking testbenches, vendor-independent, under the CERN-O…
The April 30, 2026 release promises streaming AI-model mapping onto Agilex FPGAs for deterministic edge inference.