The April 30, 2026 release promises streaming AI-model mapping onto Agilex FPGAs for deterministic edge inference.
Intel / AlteraFPGA + SoC
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The Lattice solution with NVIDIA Holoscan Sensor Bridge combines a CertusPro-NX sensor-to-Ethernet board with an edge AI data path.
LatticeFPGA + SoC
Lattice announced an Embedded Vision Summit 2026 demo program and expert session around edge AI, computer vision, sensor bridging, and robotics.
LatticeFPGA + SoC
FPGA.camp opened its first version as a compact engineering hub: news, journal, projects, classifieds, meetups, boards, KB, and Chat.
EducationOpen-sourceVerilog / SystemVerilog
Starter Tang board on Gowin GW1NR-9: 8640 LUT4, HDMI, TF slot, USB-JTAG, and USB-UART.
SipeedGowinEducation
GW2AR-18 board: 20736 LUT4, SDR SDRAM, HDMI, TF slot, and BL616 debugger.
SipeedGowinEducation
23x18 mm core board on GW5A-LV25MG121 plus dock with USB-C debugger, PMOD, and SDRAM connector.
SipeedGowinFPGA + SoC
Yosys is a baseline open-source framework for Verilog RTL synthesis and formal-related flows.
Open-sourceYosysVerilog / SystemVerilog
nextpnr supports multiple FPGA families, including Gowin through Project Apicula.
Open-sourceYosysGowin
Verilator compiles Verilog/SystemVerilog into C++/SystemC and is used in regression flows.
Open-sourceVerilatorVerilog / SystemVerilog