Start diagnostic
Placement test maps role to skills, lessons and tasks.
edu.fpga.camp
edu.fpga.camp v1
Choose a route, practice locally, and use bounded checks for HDL, simulation, constraints, boards, projects, and educator workflows.
Start here
Use the diagnostic if you are choosing a path. Use Challenges when you want a concrete local task with report.json validation.
Practical tools
Short entry points for common FPGA learning jobs: placement, practice, validation, and course material.
FPGA Challenges
4 tasks4 local checkersreport.json
Verifiable engineering tasks for HDL, simulation, constraints, timing, CDC, and EDA reports.
HDL Practice Lab
75 seeded tasks with deterministic profiles.
Educator toolkit
Read-only v1 labs, rubrics and course plans.
Learning paths
Pick the path that matches your background, then open the roadmap at the matching section.
FPGA from zero
D1beginner
Concepts, first HDL, simulation and waveform reading.
Embedded/software to FPGA
D2embeddedsoftware
Translate sequential programming habits into clocked hardware thinking.
Verilog fundamentals
D2studentjunior
Verilog combinational and sequential exercises with deterministic tests.
VHDL fundamentals
D2studentjunior
VHDL entity, process, numeric_std and simulation basics.
Simulation and verification basics
D2studentjunior
Debug with testbenches, logs and waveforms before touching a board.
Constraints and timing basics
D3juniormiddle
Clock constraints, port matching, setup/hold/slack and safe limitations.
Open-source FPGA flow
D3open-sourcejunior
Icarus, GHDL, Verilator and curated Yosys examples without vendor cloud tools.
Educator lab path
D2educator
Ready labs, rubrics and course plans for 4/8/12 week classes.