Counter with enable and reset
A basic HDL task: implement a parameterized counter and verify reset, enable, and rollover in local simulation.
D1 · 25–45 min · iverilog, verilator
Local checker available
Local challenges
Practice on your computer. Task packages and report.json validation.
How results are checked
Run this challenge on your computer. The site validates the structure of report.json. A submitted report alone does not prove that the task was completed.
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FIFO and simulation scoreboard
A local FIFO simulation task: verify data order, full/empty behavior, and no reads from an empty queue.
D2 · 45–90 min · iverilog, verilator
Local checker available
Two-flop CDC synchronizer
A CDC task: implement a safe 2FF synchronizer, check reset assumptions, and record proof limitations.
D3 · 50–110 min · verilator, symbiyosys
Local checker available
Clock constraint and timing summary
A constraints task: define a clock, run a local timing flow, and interpret pass/fail without uploading vendor logs.
D3 · 60–120 min · yosys, nextpnr, vivado
Local checker available