FPGA foundations
Ten short exercises: one HDL module or an engineering answer. Start in order or choose a topic.
Loading progress…
10 exercises
01Connect a signalassign describes a connection that is active continuously.02Select one of two inputsA multiplexer selects a signal.03Add three bitsThree one-bit inputs can sum to 3.04Store a byteA synchronous reset takes effect at the active clock edge.05Count with an enableReset has priority over enable.06Shift a serial inputFor a four-bit register, {q[2:0], din} keeps the lower three bits and appends the new bit.07Preserve the carryAn intermediate eight-bit wire truncates the carry before assignment to a wider output.08Read a waveformRead reset at the clock edge, not between edges.09Describe the clockThe period is the time between consecutive active edges.10Calculate setup slackSetup slack = required arrival time − actual arrival time.