Examples and references
Extra examples and references. They are outside the ten assessed exercises and do not add completion credit.
66 resources
Verilog demuxVerilog comparatorVerilog edge detectorVerilog debounceVerilog PWM generatorVerilog FSM traffic lightUART TX fragmentSPI fragmentSimple FIFO basicsAvoid inferred latchSigned comparatorReady/valid pass-throughMinimal testbench clock/resetVHDL entity assignmentVHDL 2:1 muxVHDL counterVHDL synchronous resetVHDL FSMVHDL shift registerVHDL numeric_std conversionVHDL avoid latchVHDL single-port RAM modelVHDL pulse generatorSystemVerilog subset always_ff counterSystemVerilog subset always_comb defaultSystemVerilog enum FSM subsetFix unused signal warningFix combinational loopFix multiple driversFix legacy sensitivity bugFix accidental latchParameterized width bug fixWaveform reading taskWaveform: counter incrementsWaveform: sync vs async resetWaveform: blocking nonblocking symptomWaveform: fsm state decodeWaveform: uart start data stopWaveform: spi mode 0 transferWaveform: pwm duty cycleWaveform: ready valid handshakeWaveform: pipeline latencyWaveform: setup violation conceptWaveform: two flop cdc traceWaveform: debouncer traceWaveform: fifo flags simplifiedWaveform: bram read latencyWaveform: signed overflowWaveform: decoder glitchWaveform: clock enable traceWaveform: reset release timingWaveform: protocol timeoutWrong port nameMissing clockGenerated clock explanationIO pin mismatchIO standard mismatchHold slackFalse path conceptMulticycle path conceptCDC basicsMatch HDL ports to constraintsCritical path in adder chainSetup vs hold violationWNS/TNS basicsObserve a saved game circuit in HDL