Project labs
Ten labs after FPGA foundations. Work with files, your own testbench and saved revisions; check behavior and inspect synthesis. Sign in to run; no board required.
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10 exercises
01Inspect digital logicCombinational outputs depend on current inputs.02Route a byte through a multiplexerA bus is several signals, not a single Boolean value.03Store a byte on a clock edgeA register samples at an edge and holds between edges.04Measure a counter and PWMCount the high samples in one full period to measure duty.05Build and debug a control FSMThe current state determines which inputs matter.06Track tokens through two stagesLatency is two sampling edges from presentation before the first edge to output after the second.07Observe FIFO occupancy and orderInspect the oldest byte, occupancy and pointer wrap together.08Transmit a UART frameObserve bit boundaries and reconstruct the byte from the waveform.09Read and write synchronous memoryThe registered output changes at the clock edge, not when the address changes.10Queue bytes for a UART transmitterThe queue absorbs bursts while TX consumes one byte per ten bit intervals.