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Learning paths

FPGA from zero

Concepts, first HDL, simulation and waveform reading.

  1. Connect a signal
  2. Select one of two inputs
  3. Add three bits
  4. Store a byte
  5. Count with an enable
  6. Shift a serial input
  7. Preserve the carry
  8. Read a waveform
  9. Describe the clock
  10. Calculate setup slack

Embedded/software to FPGA

Translate sequential programming habits into clocked hardware thinking.

  1. Verilog PWM generator · ungraded
  2. Ready/valid pass-through · ungraded
  3. Waveform: pipeline latency · ungraded

Verilog fundamentals

Verilog combinational and sequential exercises with deterministic tests.

  1. Add three bits
  2. Shift a serial input
  3. Preserve the carry

VHDL fundamentals

VHDL entity, process, numeric_std and simulation basics.

  1. VHDL entity assignment · ungraded
  2. VHDL counter · ungraded
  3. VHDL numeric_std conversion · ungraded

Simulation and verification basics

Debug with testbenches, logs and waveforms before touching a board.

  1. Minimal testbench clock/reset · ungraded
  2. Read a waveform
  3. Waveform: fsm state decode · ungraded

Constraints and timing basics

Clock constraints, port matching, setup/hold/slack and safe limitations.

  1. Describe the clock
  2. Match HDL ports to constraints · ungraded
  3. Setup vs hold violation · ungraded

Open-source FPGA flow

Icarus, GHDL, Verilator and curated Yosys examples without vendor cloud tools.

  1. Fix unused signal warning · ungraded
  2. Fix combinational loop · ungraded
  3. Describe the clock

Educator lab path

Ready labs, rubrics and course plans for 4/8/12 week classes.

  1. Connect a signal
  2. Count with an enable
  3. Read a waveform