UART TX/RX
Build a staged UART TX/RX learning project with simulation and debug checkpoints.
Plans for independent projects. You prepare the checks, constraints and testbench; these are not ready-made assessed labs.
Build a staged UART TX/RX learning project with simulation and debug checkpoints.
Build a staged SPI master learning project with simulation and debug checkpoints.
Build a staged PWM learning project with simulation and debug checkpoints.
Build a staged VGA/simple video timing learning project with simulation and debug checkpoints.
Build a staged Audio/PDM or simple FIR learning project with simulation and debug checkpoints.
Build a staged Simple CPU / tiny softcore learning project with simulation and debug checkpoints.
Build a staged RISC-V softcore intro learning project with simulation and debug checkpoints.
Build a staged Simple SoC intro learning project with simulation and debug checkpoints.