1. Interface and timing sketch
Explain clocks, reset and IO assumptions.
Audio/PDM or simple FIR
Build a staged Audio/PDM or simple FIR learning project with simulation and debug checkpoints.
2. Core HDL behavior
Simulation passes deterministic tests.
3. Debug checklist and board variant
Constraints are checked as educational examples, not signoff.
Completion criteria
All staged checks pass and final report lists limitations.
tang-nano-20kicebreaker-ice40arty-a7