FIFO and simulation scoreboard
A local FIFO simulation task: verify data order, full/empty behavior, and no reads from an empty queue.
D2 · 45–90 min · iverilog, verilator
How results are checked
Run this challenge on your computer. The site validates the structure of report.json. A submitted report alone does not prove that the task was completed.
Goal and prerequisites
- Build a scoreboard without reading private DUT internals.
- Separate a functional pass from coverage-related warnings.
- Decide which messages are safe to include in report.json.
- Basic valid/ready or write/read-enable handshake signals.
- Experience running an HDL testbench.
Challenge package
Version, licence and checksum
CC-BY-4.0 · MIT · FPGA.camp
- version
- 1.0.0
- size
- 303 bytes
- sha256
- 05764311d13fe6a90dae295b7acf2cc712a823d655f1dbeb7ca329a2d36187ec
Run locally
SystemVerilog simulation
make sim
Scoreboard check and report.json generation
make check
Criteria and common mistakes
Scoring rubric
| id | criterion | points | required | evidence_path |
|---|---|---|---|---|
| order | Data order is preserved | 35 | yes | checks.order |
| flags | full/empty flags are correct | 35 | yes | checks.flags |
| illegal-ops | Illegal reads and writes are detected | 30 | no | checks.illegal_ops |
- Comparing scoreboard data before the handshake has completed.
- Checking full/empty only immediately after reset.
- Copying a long simulator log into report.json instead of a short verdict.
Validate report.json
Choose a local check report, up to 512 KB. Source code and archives are not needed.