Counter with enable and reset
A basic HDL task: implement a parameterized counter and verify reset, enable, and rollover in local simulation.
D1 · 25–45 min · iverilog, verilator
How results are checked
Run this challenge on your computer. The site validates the structure of report.json. A submitted report alone does not prove that the task was completed.
Goal and prerequisites
- Separate synchronous reset and enable behavior in sequential logic.
- Write a minimal testbench for counter boundary states.
- Read a local checker report.json without exposing HDL to the server.
- Understanding of a clocked always block.
- Basic Verilog and local simulation workflow.
Challenge package
Version, licence and checksum
CC-BY-4.0 · MIT · FPGA.camp
- version
- 1.0.0
- size
- 295 bytes
- sha256
- faf6c1ca5f3ac16e639b98a7768bb5b299aedb5b61fd3be413ee50618760612f
Run locally
Icarus Verilog simulation
make sim TOOL=iverilog
Verilator lint
make lint TOOL=verilator
Local check and report.json generation
make check
Criteria and common mistakes
Scoring rubric
| id | criterion | points | required | evidence_path |
|---|---|---|---|---|
| reset-behavior | Reset drives the counter to zero | 30 | yes | checks.reset_behavior |
| enable-hold | The value is held when enable is 0 | 30 | yes | checks.enable_hold |
| rollover | Rollover matches the configured width | 40 | yes | checks.rollover |
- Adding an asynchronous reset when the task requires a synchronous reset.
- Checking enable behavior for only one clock cycle.
- Ending the testbench before rollover is reached.
Validate report.json
Choose a local check report, up to 512 KB. Source code and archives are not needed.