LiteX builds FPGA cores and SoCs and supports mixed-language integration around a Python flow.
Open-sourceLiteXRISC-V
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The classifieds section includes source-linked FPGA job cards: NTC Raduga, MTUCI, and Informtest.
Verilog / SystemVerilog
The /chat section accepts FPGA questions and sends them through a server-side OpenRouter endpoint.
EducationVerilog / SystemVerilog
The April 30, 2026 webinar compares when high-level code is enough and when dedicated hardware logic in Verilog is the right tool.
MicrochipEducationVerilog / SystemVerilog
PIC16F13276 and PIC18-Q35 combine an MCU with CPLD-like programmable logic for timing-critical embedded work.
MicrochipFPGA + SoC
AMD’s new engineering article covers system-level verification for Versal designs that combine PL, AI Engines, NoC, and software.
AMD / XilinxEducationVerilog / SystemVerilog
Agilex, MAX 10, and Cyclone V get planned long-term support that matters for industrial, aerospace, medical, and transportation systems.
Intel / AlteraFPGA + SoC
The April 2, 2026 Lattice webinar explains how to design FPGA acceleration for edge, data center, and server workloads.
LatticeFPGA + SoCOnline
The Vitis 2025.2 tutorial shows a system FIR flow for Versal with AI Engines, HLS, and programmable logic.
AMD / XilinxEducationFPGA + SoC
AN4792 describes a high-speed data transfer demo on PolarFire FPGA using LiteFast IP, 8b10b mode, and a loopback setup.
MicrochipEducationFPGA + SoC