On 28 September 2026 Al Williams opened The FPGA Chronicles on Hackaday: an updated FPGA Bootcamp built around the Sipeed Tang Nano 20K board with a G…
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Starter Tang board on Gowin GW1NR-9: 8640 LUT4, HDMI, TF slot, USB-JTAG, and USB-UART.
GW2AR-18 board: 20736 LUT4, SDR SDRAM, HDMI, TF slot, and BL616 debugger.
23x18 mm core board on GW5A-LV25MG121 plus dock with USB-C debugger, PMOD, and SDRAM connector.
Yosys is a baseline open-source framework for Verilog RTL synthesis and formal-related flows.
nextpnr supports multiple FPGA families, including Gowin through Project Apicula.
Verilator compiles Verilog/SystemVerilog into C++/SystemC and is used in regression flows.
LiteX builds FPGA cores and SoCs and supports mixed-language integration around a Python flow.
AMD’s new engineering article covers system-level verification for Versal designs that combine PL, AI Engines, NoC, and software.
The Vitis 2025.2 tutorial shows a system FIR flow for Versal with AI Engines, HLS, and programmable logic.