FPGA guides

Yosys is a baseline open-source framework for Verilog RTL synthesis and formal-related flows.

nextpnr supports multiple FPGA families, including Gowin through Project Apicula.

Verilator compiles Verilog/SystemVerilog into C++/SystemC and is used in regression flows.

LiteX builds FPGA cores and SoCs and supports mixed-language integration around a Python flow.