Compare boards
Up to four boards side by side: chip, logic, toolchains, interfaces and price.
| Attribute | Nexys A7 | Tang Nano 9K | Tang Mega 60K Dock |
|---|---|---|---|
| FPGA | XC7A100T-1CSG324C | GW1NR-LV9QN88PC6/I5 | GW5AT-LV60PG484AC1/I0 |
| Family | Artix-7 | GW1NR | GW5A |
| Logic (LUTs) | not listed | 8640 | 59904 |
| Price | at the seller | 14.5 USD | at the seller |
| Open toolchain | Project X-Ray / openXC7 | Project Apicula | no |
| Toolchains | Vivado WebPACK / ML Standard | Gowin EDA, Yosys + nextpnr-gowin + Apicula | Gowin EDA, LiteX (litex-boards sipeed_tang_mega_60k), openFPGALoader (GW5AT-60) |
| Interfaces | Ethernet, VGA, USB | HDMI, USB Type-C, Onboard JTAG, USB UART | PCIe 2.0 card-edge (x1 mode only at present), USB 3.0 (CH569, 5 Gbps), Gigabit Ethernet, HDMI/DVI (TX and RX), SD slot (1-bit SDIO/MMC or SPI), USB JTAG, USB UART, Differential ADC channels |
| Memory | DDR2 requires verification from Digilent resource center | PSRAM 64 Mbit, Onboard flash 32 Mbit | DDR3 4 Gbit (512 MB), Onboard flash 64 Mbit |
| Level | Beginner | Beginner | Professional |
| Where to get help | Digilent Forum | r/GowinFPGA | Sipeed forum, r/GowinFPGA |
| Known issues | — | Open-source flow is feature-dependent | PCIe works in x1 mode only; Minimum Gowin IDE version; 3.3 V I/O limit |