Compare boards
Up to four boards side by side: chip, logic, toolchains, interfaces and price.
| Attribute | Xyloni | Tang Mega 60K Dock | GW2A-18 Starter Kit | MicroZed |
|---|---|---|---|---|
| FPGA | T8F81C2 | GW5AT-LV60PG484AC1/I0 | GW2A-LV18PG256C8I7 | XC7Z010-1CLG400C |
| Family | Trion | GW5A | GW2A | Zynq-7000 |
| Logic (LUTs) | not listed | 59904 | not listed | not listed |
| Price | at the seller | at the seller | at the seller | at the seller |
| Open toolchain | no | no | Project Apicula | Project X-Ray / openXC7 |
| Toolchains | Efinity | Gowin EDA, LiteX (litex-boards sipeed_tang_mega_60k), openFPGALoader (GW5AT-60) | Gowin EDA, Project Apicula | AMD Vivado, Project X-Ray / openXC7 |
| Interfaces | not listed | PCIe 2.0 card-edge (x1 mode only at present), USB 3.0 (CH569, 5 Gbps), Gigabit Ethernet, HDMI/DVI (TX and RX), SD slot (1-bit SDIO/MMC or SPI), USB JTAG, USB UART, Differential ADC channels | Ethernet | Ethernet |
| Memory | not listed | DDR3 4 Gbit (512 MB), Onboard flash 64 Mbit | not listed | not listed |
| Level | Intermediate | Professional | Intermediate | Intermediate |
| Where to get help | official docs | Sipeed forum, r/GowinFPGA | official docs | official docs |
| Known issues | — | PCIe works in x1 mode only; Minimum Gowin IDE version; 3.3 V I/O limit | — | — |