Compare boards
Up to four boards side by side: chip, logic, toolchains, interfaces and price.
| Attribute | ECP5 Versa Development Kit | MicroZed | Tang Mega 60K Dock | LIFCL-40-EVN |
|---|---|---|---|---|
| FPGA | LFE5UM-45F | XC7Z010-1CLG400C | GW5AT-LV60PG484AC1/I0 | LIFCL-40-9BG400C |
| Family | ECP5 | Zynq-7000 | GW5A | LIFCL |
| Logic (LUTs) | not listed | not listed | 59904 | not listed |
| Price | at the seller | at the seller | at the seller | at the seller |
| Open toolchain | Project Trellis | Project X-Ray / openXC7 | no | no |
| Toolchains | Lattice Diamond, Yosys + nextpnr + Project Trellis | AMD Vivado, Project X-Ray / openXC7 | Gowin EDA, LiteX (litex-boards sipeed_tang_mega_60k), openFPGALoader (GW5AT-60) | Lattice Radiant |
| Interfaces | Ethernet, PCIe | Ethernet | PCIe 2.0 card-edge (x1 mode only at present), USB 3.0 (CH569, 5 Gbps), Gigabit Ethernet, HDMI/DVI (TX and RX), SD slot (1-bit SDIO/MMC or SPI), USB JTAG, USB UART, Differential ADC channels | MIPI_CSI |
| Memory | not listed | not listed | DDR3 4 Gbit (512 MB), Onboard flash 64 Mbit | not listed |
| Level | Professional | Intermediate | Professional | Intermediate |
| Where to get help | YosysHQ open-source tooling | official docs | Sipeed forum, r/GowinFPGA | official docs |
| Known issues | — | — | PCIe works in x1 mode only; Minimum Gowin IDE version; 3.3 V I/O limit | — |