Compare boards
Up to four boards side by side: chip, logic, toolchains, interfaces and price.
| Attribute | DE10-Lite | Arty A7 | Tang Nano 9K | Nexys A7 |
|---|---|---|---|---|
| FPGA | 10M50DAF484C7G | XC7A35TICSG324-1L | GW1NR-LV9QN88PC6/I5 | XC7A100T-1CSG324C |
| Family | MAX 10 | Artix-7 | GW1NR | Artix-7 |
| Logic (LUTs) | not listed | not listed | 8640 | not listed |
| Price | at the seller | at the seller | 14.5 USD | at the seller |
| Open toolchain | no | Project X-Ray / openXC7 | Project Apicula | Project X-Ray / openXC7 |
| Toolchains | Intel Quartus Prime | Vivado WebPACK / ML Standard | Gowin EDA, Yosys + nextpnr-gowin + Apicula | Vivado WebPACK / ML Standard |
| Interfaces | VGA, USB-Blaster | Ethernet, USB UART, USB-JTAG | HDMI, USB Type-C, Onboard JTAG, USB UART | Ethernet, VGA, USB |
| Memory | SDRAM requires Terasic manual verification | DDR3 variant-specific; verify in Digilent memory tab | PSRAM 64 Mbit, Onboard flash 32 Mbit | DDR2 requires verification from Digilent resource center |
| Level | Beginner | Beginner | Beginner | Beginner |
| Where to get help | Terasic support | Digilent Forum | r/GowinFPGA | Digilent Forum |
| Known issues | — | 35T and 100T variants differ | Open-source flow is feature-dependent | — |