The license requires manual review.
BaseJump STL
Reusable SystemVerilog library.
Buses and infrastructureNo license foundM2 · Simulation-testedupdated 9 days ago
Worth knowing
Facts
From GitHub data, checked October 7, 2026.
- Maturity
- M2 · Simulation-tested
- License
- No license found
- Tests
- yes
- CI
- not found
- Formal verification
- not found
- FuseSoC
- not found
- Last commit
- updated 9 days ago
- Stars
- 689
The repository contains tests or a testbench. How maturity is assigned
Purpose
Verilator
Boards
No one has confirmed a board run yet.
Add evidenceSources
- BaseJump STL source · 2026-04-30
How to check it locally
- Run the upstream simulation/test command from the repository README or CI workflow.
- Try a synthesis smoke run with: Verilator.
Scores and how they are computed
License, tests, CI, formal checks, documentation and activity come from the repository check. Usefulness and learning value are editorial estimates.
Quality55
Verification45
License15
Docs70
Integration35
Usefulness54
Beginner42
Professional50
Confidence40
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