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Up to four cores side by side: maturity, license, tests and activity.

Attributecdc_utilstaxiverilog-axi
MaturityM1 · PrototypeM2 · Simulation-testedM2 · Simulation-tested
LicenseNo license foundCERN-OHL-S-2.0 · CopyleftMIT · Commercial-friendly
Language———
Tests—yesyes
CI—yesyes
Formal———
FuseSoC———
Activity—updated 40 days agoupdated 2 years ago
Boards———
Interfaces—FIFO/stream, AXIAXI
CategoryBuses and infrastructureBuses and infrastructureBuses and infrastructure

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