Compare cores

Up to four cores side by side: maturity, license, tests and activity.

Attributecdc_utilstaxiverilog-axisverilog-axi
MaturityM1 · PrototypeM2 · Simulation-testedM2 · Simulation-testedM2 · Simulation-tested
LicenseNo license foundCERN-OHL-S-2.0 · CopyleftMIT · Commercial-friendlyMIT · Commercial-friendly
Language————
Tests—yesyesyes
CI—yesyesyes
Formal————
FuseSoC————
Activity—updated 40 days agoupdated 2 years agoupdated 2 years ago
Boards————
Interfaces—FIFO/stream, AXIFIFO/stream, AXIAXI
CategoryBuses and infrastructureBuses and infrastructureBuses and infrastructureBuses and infrastructure