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Up to four cores side by side: maturity, license, tests and activity.

Attributecdc_utilsverilog-axistaxi
MaturityM1 · PrototypeM2 · Simulation-testedM2 · Simulation-tested
LicenseNo license foundMIT · Commercial-friendlyCERN-OHL-S-2.0 · Copyleft
Language———
Tests—yesyes
CI—yesyes
Formal———
FuseSoC———
Activity—updated 2 years agoupdated 40 days ago
Boards———
Interfaces—FIFO/stream, AXIFIFO/stream, AXI
CategoryBuses and infrastructureBuses and infrastructureBuses and infrastructure

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