Compare cores
Up to four cores side by side: maturity, license, tests and activity.
| Attribute | opencores pwm | verilog-ethernet | uart verilog by alexforencich |
|---|---|---|---|
| Maturity | M1 · Prototype | M2 · Simulation-tested | M2 · Simulation-tested |
| License | No license found | MIT · Commercial-friendly | MIT · Commercial-friendly |
| Language | Verilog/VHDL unknown until review | — | — |
| Tests | — | yes | yes |
| CI | — | yes | yes |
| Formal | — | — | — |
| FuseSoC | — | — | — |
| Activity | — | updated 2 years ago | updated 2 years ago |
| Boards | — | — | — |
| Interfaces | PWM | Ethernet | UART |
| Category | Interfaces and peripherals | Interfaces and peripherals | Interfaces and peripherals |