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Up to four cores side by side: maturity, license, tests and activity.

Attributeultraembedded riscvSERV
MaturityM2 · Simulation-testedM4 · Production-ready
LicenseBSD-3-Clause · Commercial-friendlyISC · Commercial-friendly
Language—Verilog
Testsyesyes
CI—yes
Formal——
FuseSoC—yes
Activityupdated 5 years agoupdated 43 days ago
Boards——
Interfaces——
CategoryCPUs and computeCPUs and compute

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