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Up to four cores side by side: maturity, license, tests and activity.

Attributeultraembedded riscvVexRiscv
MaturityM2 · Simulation-testedM2 · Simulation-tested
LicenseBSD-3-Clause · Commercial-friendlyMIT · Commercial-friendly
Language—SpinalHDL/Scala/Verilog
Testsyesyes
CI—yes
Formal——
FuseSoC——
Activityupdated 5 years agoupdated 10 days ago
Boards——
Interfaces——
CategoryCPUs and computeCPUs and compute

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