Compare cores

Up to four cores side by side: maturity, license, tests and activity.

Attributeverilog-spiOpenTitan UART IPverilog-ethernet
MaturityM1 · PrototypeM4 · Production-readyM2 · Simulation-tested
LicenseNo license foundApache-2.0 · Commercial-friendlyMIT · Commercial-friendly
Language———
Tests—yesyes
CI—yesyes
Formal———
FuseSoC—yes—
Activity—updated 1 day agoupdated 2 years ago
Boards———
InterfacesSPI/QSPIUARTEthernet
CategoryInterfaces and peripheralsInterfaces and peripheralsInterfaces and peripherals

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