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Up to four cores side by side: maturity, license, tests and activity.

Attributeverilog-spiverilog-ethernet
MaturityM1 · PrototypeM2 · Simulation-tested
LicenseNo license foundMIT · Commercial-friendly
Language——
Tests—yes
CI—yes
Formal——
FuseSoC——
Activity—updated 2 years ago
Boards——
InterfacesSPI/QSPIEthernet
CategoryInterfaces and peripheralsInterfaces and peripherals

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