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Up to four cores side by side: maturity, license, tests and activity.

AttributeWally RISC-VVexRiscv
MaturityM4 · Production-readyM2 · Simulation-tested
LicenseNo license foundMIT · Commercial-friendly
LanguageSystemVerilogSpinalHDL/Scala/Verilog
Testsyesyes
CIyesyes
Formal——
FuseSoC——
Activityupdated todayupdated 10 days ago
Boards——
Interfaces——
CategoryCPUs and computeCPUs and compute

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