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Up to four cores side by side: maturity, license, tests and activity.

Attributewb_ramLiteDRAM
MaturityM1 · PrototypeM2 · Simulation-tested
LicenseNo license foundNo license found
Language—Migen/Python/Verilog
Tests—yes
CI—yes
Formal——
FuseSoC——
Activity—updated 7 days ago
Boards——
InterfacesMemory, WishboneMemory
CategoryMemory and storageMemory and storage

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