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jotego jtcores
Large curated arcade FPGA core ecosystem.
RetroVerilogGPL-3.0M2 · Simulation-testedupdated 3 days ago
Worth knowing
Facts
From GitHub data, checked October 5, 2026.
- Maturity
- M2 · Simulation-tested
- License
- GPL-3.0 · Copyleft
- Tests
- yes
- CI
- yes
- Formal verification
- not found
- FuseSoC
- not found
- Last commit
- updated 3 days ago
- Stars
- 338
The repository contains tests or a testbench. How maturity is assigned
Purpose
Verilator
Boards
No one has confirmed a board run yet.
Add evidenceSources
- jotego jtcores source · 2026-04-30
How to check it locally
- Run the upstream simulation/test command from the repository README or CI workflow.
- Try a synthesis smoke run with: Verilator.
Scores and how they are computed
License, tests, CI, formal checks, documentation and activity come from the repository check. Usefulness and learning value are editorial estimates.
Quality70
Verification65
License55
Docs70
Integration35
Usefulness72
Beginner42
Professional68
Confidence40
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