Sign in

LitePCIe

Open PCIe ecosystem core.

Interfaces and peripheralsMigen/Python/VerilogNo license foundM2 · Simulation-testedupdated 9 days ago

RepositoryCompareAsk in Chat

Worth knowing

Warning

The license requires manual review.

High

There is a vendor tooling or license constraint.

Facts

From GitHub data, checked October 6, 2026.

Maturity
M2 · Simulation-tested
License
No license found
Tests
yes
CI
yes
Formal verification
not found
FuseSoC
not found
Last commit
updated 9 days ago
Stars
732

The repository contains tests or a testbench. How maturity is assigned

Purpose

PCIeLiteXVerilator

Boards

No one has confirmed a board run yet.

Add evidence

Sources

How to check it locally
  • Run the upstream simulation/test command from the repository README or CI workflow.
  • Try a synthesis smoke run with: LiteX, Verilator.
Scores and how they are computed

License, tests, CI, formal checks, documentation and activity come from the repository check. Usefulness and learning value are editorial estimates.

Quality60
Verification65
License15
Docs70
Integration35
Usefulness72
Beginner42
Professional63
Confidence40

Similar cores