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verilog-pcie

PCIe endpoint/DMA candidate.

Interfaces and peripheralsMITM2 · Simulation-testedupdated 2 years ago

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Worth knowing

High

There is a vendor tooling or license constraint.

Facts

From GitHub data, checked October 7, 2026.

Maturity
M2 · Simulation-tested
License
MIT · Commercial-friendly
Tests
yes
CI
yes
Formal verification
not found
FuseSoC
not found
Last commit
updated 2 years ago
Stars
1666

The repository contains tests or a testbench. How maturity is assigned

Purpose

PCIeVerilator

Boards

No one has confirmed a board run yet.

Add evidence

Sources

How to check it locally
  • Run the upstream simulation/test command from the repository README or CI workflow.
  • Try a synthesis smoke run with: Verilator.
Scores and how they are computed

License, tests, CI, formal checks, documentation and activity come from the repository check. Usefulness and learning value are editorial estimates.

Quality71
Verification65
License90
Docs70
Integration35
Usefulness54
Beginner42
Professional68
Confidence40

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