ZipCPU wb2axip

Wishbone/AXI bridge and formal property library.

Buses and infrastructureVerilogNo license foundM2 · Simulation-testedupdated 26 days ago

Worth knowing

Warning

The license requires manual review.

Facts

From GitHub data, checked October 5, 2026.

Maturity
M2 · Simulation-tested
License
No license found
Tests
yes
CI
not found
Formal verification
yes
FuseSoC
yes
Last commit
updated 26 days ago
Stars
706

The repository contains tests or a testbench. How maturity is assigned

Purpose

WishboneAXIVerilator

Boards

No one has confirmed a board run yet.

Add evidence

Sources

How to check it locally
  • Run the upstream simulation/test command from the repository README or CI workflow.
  • Inspect the upstream FuseSoC .core manifest and use it as the integration entrypoint.
  • Try a synthesis smoke run with: Verilator.
Scores and how they are computed

License, tests, CI, formal checks, documentation and activity come from the repository check. Usefulness and learning value are editorial estimates.

Quality60
Verification65
License15
Docs70
Integration75
Usefulness72
Beginner42
Professional63
Confidence40

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