Verilator

Open-source SystemVerilog simulator and lint system.

Verilator is a fast simulation and lint tool for regression flows.

The card links to the official project repository.

More projects

Maintainedgithub.comMay 8, 2026Apache-2.0

Suite of SystemVerilog developer tools: parser, formatter, linter, and syntax tooling.

Maintainedgitlab.comMay 8, 2026EUPL-1.2

Extensible waveform viewer for VCD/FST/GHW debug, available as native and web apps.

Maintainedgithub.comApril 26, 2026ISC

Open SYnthesis Suite for Verilog RTL synthesis and formal-related flows.

VerilogRTLILSynthesisFormalOpen-source Yosys+1