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Up to four boards side by side: chip, logic, toolchains, interfaces and price.

AttributeTang Nano 20KiCEBreakerTang Nano 9KTang Mega 60K Dock
FPGAGW2AR-LV18QN88C8/I7iCE40UP5K-SG48GW1NR-LV9QN88PC6/I5GW5AT-LV60PG484AC1/I0
FamilyGW2ARiCE40 UltraPlusGW1NRGW5A
Logic (LUTs)207365280864059904
Price28.17 USDat the seller14.5 USDat the seller
Open toolchainProject ApiculaProject IceStormProject Apiculano
ToolchainsGowin EDA, Yosys + nextpnr-gowin + ApiculaYosys + nextpnr + IceStorm, Lattice Diamond ProgrammerGowin EDA, Yosys + nextpnr-gowin + ApiculaGowin EDA, LiteX (litex-boards sipeed_tang_mega_60k), openFPGALoader (GW5AT-60)
InterfacesHDMI, MAX98357A I2S amplifier path, TF card slot, USB Type-C, Onboard BL616 JTAG, USB UARTmicroUSB FT2232H, FT2232H programming, USB serialHDMI, USB Type-C, Onboard JTAG, USB UARTPCIe 2.0 card-edge (x1 mode only at present), USB 3.0 (CH569, 5 Gbps), Gigabit Ethernet, HDMI/DVI (TX and RX), SD slot (1-bit SDIO/MMC or SPI), USB JTAG, USB UART, Differential ADC channels
Memory32-bit SDR SDRAM 64 Mbit, Onboard flash 64 MbitQSPI flash 128 MbitPSRAM 64 Mbit, Onboard flash 32 MbitDDR3 4 Gbit (512 MB), Onboard flash 64 Mbit
LevelBeginnerBeginnerBeginnerProfessional
Where to get helpSipeed forum, r/GowinFPGAiCEBreaker community docsr/GowinFPGASipeed forum, r/GowinFPGA
Known issuesOnboard debugger recognition; Flash persistence mode—Open-source flow is feature-dependentPCIe works in x1 mode only; Minimum Gowin IDE version; 3.3 V I/O limit