Tang Nano 20K

An FPGA is configurable digital logic: the design becomes hardware structure after synthesis, place-and-route and bitstream generation.

Pick the first board by toolchain access, verified examples, documentation, community help and a realistic first project.

Constraint files bind logical ports to package pins and define clocks, I/O standards and timing assumptions.

The practical FPGA flow is lint/simulation, synthesis, constraints, place-and-route, timing, bitstream, programming and board validation.

Yosys is an open-source synthesis tool; nextpnr is a portable place-and-route tool supporting several FPGA architectures through device databases.

Gowin EDA is the vendor flow for Gowin FPGA families used by Tang and Gowin starter boards.

Start with board recognition, exact device selection, LED example, flash/SRAM programming distinction and board-revision pinout check.

FPGA order codes encode family, density, package, speed grade, temperature range and sometimes feature variants.

UART is the simplest board-visible debug channel, but it still needs clock-derived baud timing, synchronizers and a testbench.

A RISC-V softcore project needs enough logic, memory, a debug path, firmware build flow and a board-specific memory/IO map.