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RISC-V softcore on FPGA

A RISC-V softcore project needs enough logic, memory, a debug path, firmware build flow and a board-specific memory/IO map.

Start with UART firmware output before adding caches, SDRAM or Linux. For Linux-capable systems, choose a board with documented external memory and an existing SoC example.

Graph links

Boards: sipeed/tang-nano-20k, radiona/ulx3s, digilent/arty-a7, terasic/de10-nano
Chips: none
Toolchains: yosys-nextpnr-trellis, vivado-webpack, gowin-eda
Protocols: uart, spi, wishbone, axi
Pitfalls: CPU demos fail silently when clock, reset or memory initialization are wrong.

Related boards

Compact Gowin GW2AR board with HDMI, audio amplifier, TF card slot, SDRAM, and onboard debugger.

Gowin Semiconductor GW2AR20,736 LUTopen toolchain28.17 USD

ULX3SRadiona / EMARD

Open-hardware Lattice ECP5 board used for open-source FPGA development, education, LiteX and retro-computing projects.

Lattice Semiconductor ECP5open toolchainprice at the seller

Arty A7Digilent

Digilent Artix-7 board with Vivado WebPACK support, Pmods, Arduino/chipKIT style expansion, DDR3 and Ethernet.

AMD/Xilinx Artix-7open toolchainprice at the seller

DE10-NanoTerasic

Terasic Cyclone V SoC board widely used for Intel FPGA education, Linux-on-SoC labs and MiSTer-style retro FPGA work.

Intel/Altera Cyclone V SoCopen toolchainprice at the seller

Sources

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