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UART in FPGA projects

UART is the simplest board-visible debug channel, but it still needs clock-derived baud timing, synchronizers and a testbench.

A UART echo is a good second project after blink. It forces clock math, serial timing, RX synchronization and a repeatable board-visible result.

Graph links

Boards: sipeed/tang-nano-20k, digilent/arty-a7, icebreaker/icebreaker
Chips: none
Toolchains: none
Protocols: uart
Pitfalls: Wrong clock frequency gives wrong baud rate. RX input must cross safely into the local clock domain.

Related boards

Compact Gowin GW2AR board with HDMI, audio amplifier, TF card slot, SDRAM, and onboard debugger.

Gowin Semiconductor GW2AR20,736 LUTopen toolchain28.17 USD

iCEBreakeriCEBreaker FPGA

Open-source educational Lattice iCE40UP5K board designed around the Yosys, nextpnr and IceStorm flow.

Lattice Semiconductor iCE40 UltraPlus5,280 LUTopen toolchainprice at the seller

Arty A7Digilent

Digilent Artix-7 board with Vivado WebPACK support, Pmods, Arduino/chipKIT style expansion, DDR3 and Ethernet.

AMD/Xilinx Artix-7open toolchainprice at the seller

Sources

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