conceptbeginnerconfidence 4/5CC BY 4.0

From HDL to bitstream

The practical FPGA flow is lint/simulation, synthesis, constraints, place-and-route, timing, bitstream, programming and board validation.

Keep each flow artifact reproducible: source HDL, constraints, project scripts, generated reports and exact tool versions. GUI-only flows are acceptable for learning, but production projects should be scriptable.

Graph links

Boards: icebreaker/icebreaker, digilent/arty-a7, sipeed/tang-nano-20k
Chips: none
Toolchains: yosys, nextpnr, vivado-webpack, quartus-prime
Protocols: none
Pitfalls: Skipping simulation shifts basic bugs into the slowest debug loop: hardware bring-up.

Related boards

Compact Gowin GW2AR board with HDMI, audio amplifier, TF card slot, SDRAM, and onboard debugger.

Gowin Semiconductor GW2AR20,736 LUTopen toolchain28.17 USD

iCEBreakeriCEBreaker FPGA

Open-source educational Lattice iCE40UP5K board designed around the Yosys, nextpnr and IceStorm flow.

Lattice Semiconductor iCE40 UltraPlus5,280 LUTopen toolchainprice at the seller

Arty A7Digilent

Digilent Artix-7 board with Vivado WebPACK support, Pmods, Arduino/chipKIT style expansion, DDR3 and Ethernet.

AMD/Xilinx Artix-7open toolchainprice at the seller

Sources

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