Compare boards
Up to four boards side by side: chip, logic, toolchains, interfaces and price.
| Attribute | DE10-Lite | Arty A7 | Tang Nano 20K | Tang Nano 9K |
|---|---|---|---|---|
| FPGA | 10M50DAF484C7G | XC7A35TICSG324-1L | GW2AR-LV18QN88C8/I7 | GW1NR-LV9QN88PC6/I5 |
| Family | MAX 10 | Artix-7 | GW2AR | GW1NR |
| Logic (LUTs) | not listed | not listed | 20736 | 8640 |
| Price | at the seller | at the seller | 28.17 USD | 14.5 USD |
| Open toolchain | no | Project X-Ray / openXC7 | Project Apicula | Project Apicula |
| Toolchains | Intel Quartus Prime | Vivado WebPACK / ML Standard | Gowin EDA, Yosys + nextpnr-gowin + Apicula | Gowin EDA, Yosys + nextpnr-gowin + Apicula |
| Interfaces | VGA, USB-Blaster | Ethernet, USB UART, USB-JTAG | HDMI, MAX98357A I2S amplifier path, TF card slot, USB Type-C, Onboard BL616 JTAG, USB UART | HDMI, USB Type-C, Onboard JTAG, USB UART |
| Memory | SDRAM requires Terasic manual verification | DDR3 variant-specific; verify in Digilent memory tab | 32-bit SDR SDRAM 64 Mbit, Onboard flash 64 Mbit | PSRAM 64 Mbit, Onboard flash 32 Mbit |
| Level | Beginner | Beginner | Beginner | Beginner |
| Where to get help | Terasic support | Digilent Forum | Sipeed forum, r/GowinFPGA | r/GowinFPGA |
| Known issues | — | 35T and 100T variants differ | Onboard debugger recognition; Flash persistence mode | Open-source flow is feature-dependent |