Compare boards
Up to four boards side by side: chip, logic, toolchains, interfaces and price.
| Attribute | DE10-Nano | Tang Nano 9K | Arty A7 | TE0890 |
|---|---|---|---|---|
| FPGA | 5CSEBA6U23I7 | GW1NR-LV9QN88PC6/I5 | XC7A35TICSG324-1L | XC7S25-1FTGB196C |
| Family | Cyclone V SoC | GW1NR | Artix-7 | Spartan-7 |
| Logic (LUTs) | not listed | 8640 | not listed | not listed |
| Price | at the seller | 14.5 USD | at the seller | at the seller |
| Open toolchain | Mistral | Project Apicula | Project X-Ray / openXC7 | Project X-Ray / openXC7 |
| Toolchains | Intel Quartus Prime | Gowin EDA, Yosys + nextpnr-gowin + Apicula | Vivado WebPACK / ML Standard | AMD Vivado, Project X-Ray / openXC7 |
| Interfaces | HDMI TX, Ethernet, USB | HDMI, USB Type-C, Onboard JTAG, USB UART | Ethernet, USB UART, USB-JTAG | not listed |
| Memory | HPS DDR3 requires Terasic manual verification | PSRAM 64 Mbit, Onboard flash 32 Mbit | DDR3 variant-specific; verify in Digilent memory tab | not listed |
| Level | Intermediate | Beginner | Beginner | Intermediate |
| Where to get help | Terasic support | r/GowinFPGA | Digilent Forum | official docs |
| Known issues | — | Open-source flow is feature-dependent | 35T and 100T variants differ | — |