This is a template/example, not a standalone core.
AccelFury core-template
FPGA IP template with a manifest, board and toolchain configuration, SPDX checks, separate licenses and a release checklist.
Generators and frameworksRust/SystemVerilog/TypeScriptCERN-OHL-S-2.0 + AGPL + CC-BY-SAM2 · Simulation-testedupdated 5 months ago
Worth knowing
Generated projects require separate review.
Facts
From GitHub data, checked October 6, 2026.
- Maturity
- M2 · Simulation-tested
- License
- CERN-OHL-S-2.0 + AGPL + CC-BY-SA · Copyleft
- Tests
- yes
- CI
- yes
- Formal verification
- not found
- FuseSoC
- not found
- Last commit
- updated 5 months ago
- Stars
- 0
The repository contains tests or a testbench. How maturity is assigned
Purpose
unknownVerilator
Boards
No one has confirmed a board run yet.
Add evidenceSources
- AccelFury core-template source · 2026-04-30
How to check it locally
- Run the upstream simulation/test command from the repository README or CI workflow.
- Try a synthesis smoke run with: Verilator.
Scores and how they are computed
License, tests, CI, formal checks, documentation and activity come from the repository check. Usefulness and learning value are editorial estimates.
Quality70
Verification65
License55
Docs70
Integration35
Usefulness36
Beginner42
Professional68
Confidence60
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