Manycore RISC-V candidate.
CPUs and computeBSD-3-ClauseM2 · Simulation-testedupdated today
From GitHub data, checked October 7, 2026.
The repository contains tests or a testbench. How maturity is assigned
No one has confirmed a board run yet.
Add evidenceLicense, tests, CI, formal checks, documentation and activity come from the repository check. Usefulness and learning value are editorial estimates.
MIT-licensed RISC-V CPU from SpinalHDL, successor of VexRiscv: RV32/64, optional SV32/SV39 MMU, Linux capable, written in SpinalHDL, generates Verilog.
CPUs and computeSpinalHDL (Scala)MITM2 · Simulation-testedupdated 9 days ago
Small open RISC-V CPU used by OpenTitan.
CPUs and computeSystemVerilogApache-2.0M2 · Simulation-testedupdated 5 days ago
Tiny RISC-V core and FuseSoC-friendly ecosystem.
CPUs and computeVerilogISCM4 · Production-readyupdated 43 days ago
