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Up to four cores side by side: maturity, license, tests and activity.

AttributeBOOMNEORV32VexiiRiscv
MaturityM1 · PrototypeM4 · Production-readyM2 · Simulation-tested
LicenseBSD-3-Clause · Commercial-friendlyBSD-3-Clause · Commercial-friendlyMIT · Commercial-friendly
Language—VHDLSpinalHDL (Scala)
Tests—yesyes
CIyesyesyes
Formal———
FuseSoC———
Activityupdated 26 days agoupdated 3 days agoupdated 1 day ago
Boards———
Interfaces——AXI4, Wishbone, Tilelink, AXI4, Wishbone, Tilelink
CategoryCPUs and computeCPUs and computeCPUs and compute

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