High-end RISC-V research core.
CPUs and computeBSD-3-ClauseM1 · Prototypeupdated 26 days ago
From GitHub data, checked October 7, 2026.
Source exists, but no tests were found. How maturity is assigned
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MIT-licensed RISC-V CPU from SpinalHDL, successor of VexRiscv: RV32/64, optional SV32/SV39 MMU, Linux capable, written in SpinalHDL, generates Verilog.
CPUs and computeSpinalHDL (Scala)MITM2 · Simulation-testedupdated 9 days ago
Small open RISC-V CPU used by OpenTitan.
CPUs and computeSystemVerilogApache-2.0M2 · Simulation-testedupdated 5 days ago
Manycore RISC-V candidate.
CPUs and computeBSD-3-ClauseM2 · Simulation-testedupdated today
