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Up to four cores side by side: maturity, license, tests and activity.

AttributeBOOMVexiiRiscv
MaturityM1 · PrototypeM2 · Simulation-tested
LicenseBSD-3-Clause · Commercial-friendlyMIT · Commercial-friendly
Language—SpinalHDL (Scala)
Tests—yes
CIyesyes
Formal——
FuseSoC——
Activityupdated 26 days agoupdated 9 days ago
Boards——
Interfaces—AXI4, Wishbone, Tilelink, AXI4, Wishbone, Tilelink
CategoryCPUs and computeCPUs and compute

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