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Up to four cores side by side: maturity, license, tests and activity.

AttributeIObundle EthernetLiteSPI
MaturityM4 · Production-readyM2 · Simulation-tested
LicenseCERN-OHL-S-2.0 · CopyleftBSD-2-Clause · Commercial-friendly
Language—Migen/Python/Verilog
Testsyesyes
CIyesyes
Formal——
FuseSoC——
Activityupdated 16 days agoupdated 13 days ago
Boards——
InterfacesEthernetSPI/QSPI
CategoryInterfaces and peripheralsInterfaces and peripherals

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