Compare cores

Up to four cores side by side: maturity, license, tests and activity.

AttributeLiteDRAMLiteSATALiteSDCardwb_ram
MaturityM2 · Simulation-testedM2 · Simulation-testedM2 · Simulation-testedM1 · Prototype
LicenseNo license foundNo license foundNo license foundNo license found
LanguageMigen/Python/VerilogMigen/Python/VerilogMigen/Python/Verilog—
Testsyesyesyes—
CIyesyesyes—
Formal————
FuseSoC————
Activityupdated 1 day agoupdated 9 days agoupdated 1 day ago—
Boards————
InterfacesMemorySATASD/SDIOMemory, Wishbone
CategoryMemory and storageMemory and storageMemory and storageMemory and storage